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Integrated Circuit Systems, Inc.
ICS952703 Preliminary Product Preview
Programmable Timing Control Hub for K7TM System
Recommended Application: SiS741 style chipset with 964 South Bridge. Features/Benefits: * Selectable synchronous/asynchronous AGP/PCI frequency * Programmable output frequency. Output Features: * Programmable output divider ratios. * 1 - Pair of differential open drain CPU outputs * Programmable output rise/fall time. * 1 - Single-ended open drain CPU output * Programmable output skew. * 1 - Pair of current mode differential serial reference clock * Programmable spread percentage for EMI control. * 8 - PCICLK @ 3.3V including 2 PCI clock free running * Watchdog timer technology to reset system * 2 - AGPCLK @ 3.3V if system malfunctions. * 3 - REF @ 3.3V * Programmable watch dog safe frequency. * 2 - ZCLK @ 3.3V * Support I2C Index read/write and block read/write * 2 - IOAPIC @ 2.5V operations. * 1 - 12_48MHz @ 3.3V * Uses external 14.318MHz reference input. * 1 - 24_48MHz @ 3.3V Key Specifications: * CPU Output Jitter <250ps * AGP Output Jitter <250ps * ZCLK Output Jitter <250ps * PCI Output Jitter <500ps * CPU-AGP/PCI/ZCLK skew: 2.5ns~3.5ns Functionality
Bit4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit3 FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit2 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit0 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU MHz 200.00 200.01 200.97 190.11 100.00 100.00 100.99 95.00 166.66 166.65 161.59 151.97 133.33 133.34 133.98 126.66 206.02 210.00 214.06 217.90 103.01 105.00 106.99 109.01 164.66 167.91 171.22 174.38 137.32 140.00 142.67 145.33 SRC MHz 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 ZCLK MHz 133.33 133.34 133.98 126.74 133.33 133.34 134.66 126.66 133.33 133.32 129.27 121.57 133.33 133.34 133.98 126.66 137.35 140.00 142.70 145.27 137.35 140.00 142.65 145.35 131.73 134.33 136.98 139.50 137.32 140.00 142.67 145.33 AGP MHz 66.66 66.67 66.99 63.37 66.66 66.67 67.33 63.33 66.66 66.66 64.64 60.79 66.66 66.67 66.99 63.33 68.67 70.00 71.35 72.63 68.67 70.00 71.33 72.68 65.86 67.17 68.49 69.75 68.66 70.00 71.34 72.66 PCI MHz 33.33 33.33 33.49 31.69 33.33 33.33 33.66 31.67 33.33 33.33 32.32 30.39 33.33 33.33 33.49 31.67 34.34 35.00 35.68 36.32 34.34 35.00 35.66 36.34 32.93 33.58 34.24 34.88 34.33 35.00 35.67 36.33
Pin Configuration
VDDREF 1 **FS0/REF0 2 **FS1/REF1 3 **Mode/REF2 4 GNDREF 5 X1 6 X2 7 GNDZ 8 ZCLK0 9 VDDZ 11 SCLK 12 VDDPCI 13 *FS2/PCICLK_F0 14 *FS3/PCICLK_F1 15 PCICLK0 16 PCICLK1 17 GNDPCI 18 VDDPCI 19 PCICLK2 20 *(PCI_STOP#)PCICLK3 21 *(CPU_STOP#)PCICLK4 22 *(PD#)PCICLK5 23 GNDPCI 24 48 VDDLAPIC 47 IOAPIC1 46 IOAPIC0 45 GNDAPIC 44 VDDSRC 43 SRCCLKT 42 SRCCLKC 41 GND
ICS952703
ZCLK1 10
40 CPUCLKODT1 39 GNDCPU 38 CPUCLKODT0 37 CPUCLKODC0 36 AVDD 35 AGND 34 IREF 33 SDATA 32 GNDAGP 31 AGPCLK0 30 AGPCLK1 29 VDDAGP 28 AVDD48 27 12_48MHz/SEL12_48#MHz* 26 24_48MHz/SEL24_48#MHz**~ 25 GND48
48-SSOP
* Internal Pull-Up Resistor ** Internal Pull-Down Resistor ~ This output have 1.5X Drive Strength
0813B--05/17/05
Integrated Circuit Systems, Inc.
ICS952703 Preliminary Product Preview
General Description
The ICS952703 is a two chip clock solution for desktop designs using SiS741 style chipsets. When used with a zero delay buffer such as the ICS9179-16 for PC133 or the ICS93735 for DDR applications it provides all the necessary clocks signals for such a system. The ICS952703 is part of a whole new line of ICS clock generators and buffers called TCHTM (Timing Control Hub). ICS is the first to introduce a whole product line which offers full programmability and flexibility on a single clock device. Employing the use of a serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. TCH also incorporates ICS's Watchdog Timer technology and a reset feature to provide a safe setting under unstable system conditions. M/N control can configure output frequency with resolution up to 0.1MHz increment.
Block Diagram
PLL2 Frequency Dividers 12_48MHZ 24_48MHZ X1 X2 CPU_STOP# PCI_STOP# SCLK SEL24_48MHZ SEL12_48MHz PD# SDATA FS (3:0) MODE Control Logic Programmable Spread PLL1 Programmable Frequency Dividers STOP Logic XTAL REF (2:0) CPUCLKODT (1:0) CPUCLKODC0 SRCCLKT SRCCLKC IOAPIC (1:0) PCICLKF (1:0) PCICLK (5:0) ZCLK (1:0) AGPCLK (1:0)
0813B--05/17/05
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ICS952703 Preliminary Product Preview
Pin Description
PIN # PIN NAME 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 VDDREF **FS0/REF0 **FS1/REF1 **Mode/REF2 GNDREF X1 X2 GNDZ ZCLK0 ZCLK1 VDDZ SCLK VDDPCI *FS2/PCICLK_F0 *FS3/PCICLK_F1 PCICLK0 PCICLK1 GNDPCI VDDPCI PCICLK2 *(PCI_STOP#)PCICLK3 *(CPU_STOP#)PCICLK4 *(PD#)PCICLK5 GNDPCI GND48 24_48MHz/SEL24_48#MHz**~ 12_48MHz/SEL12_48#MHz* AVDD48 VDDAGP AGPCLK1 AGPCLK0 GNDAGP SDATA IREF AGND AVDD CPUCLKODC0 CPUCLKODT0 GNDCPU CPUCLKODT1 GND SRCCLKC SRCCLKT VDDSRC GNDAPIC IOAPIC0 IOAPIC1 VDDLAPIC PIN TYPE PWR I/O I/O I/O PWR IN OUT PWR OUT OUT PWR IN PWR I/O I/O OUT OUT PWR PWR OUT I/O I/O I/O PWR PWR I/O I/O PWR PWR OUT OUT PWR I/O OUT PWR PWR OUT OUT PWR OUT PWR OUT OUT PWR PWR OUT OUT PWR DESCRIPTION Ref, XTAL power supply, nominal 3.3V Frequency select latch input pin / 14.318 MHz reference clock. Frequency select latch input pin / 14.318 MHz reference clock. Function select latch input pin, 0=Desktop Mode, 1=Mobile Mode / Ref clock output. Ground pin for the REF outputs. Crystal input, Nominally 14.318MHz. Crystal output, Nominally 14.318MHz Ground pin for the ZCLK outputs 3.3V Hyperzip clock output. 3.3V Hyperzip clock output. Power supply for ZCLK clocks, nominal 3.3V Clock pin of I2C circuitry 5V tolerant Power supply for PCI clocks, nominal 3.3V Frequency select latch input pin / 3.3V PCI free running clock output. Frequency select latch input pin / 3.3V PCI free running clock output. PCI clock output. PCI clock output. Ground pin for the PCI outputs Power supply for PCI clocks, nominal 3.3V PCI clock output. Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input low. This input is activated by the MODE selection pin / PCI clock output. Stops all CPUCLKs besides the CPUCLK_F clocks at logic 0 level, when input low. This input is activated by the MODE selection pin / PCI clock output. Asynchronous active low input pin used to power down the device into a low power state / PCI clock output. Ground pin for the PCI outputs Ground pin for the 48MHz outputs 24/48MHz clock output / Latched select input for 24/48MHz output. 0=48MHz, 1 = 24MHz. 12/48MHz clock output / Latched select input for 12/48MHz output. 0=48MHz, 1 = 12MHz. Power for 24/48MHz outputs and fixed PLL core, nominal 3.3V Power supply for AGP clocks, nominal 3.3V AGP clock output AGP clock output Ground pin for the AGP outputs Data pin for I2C circuitry 5V tolerant This pin establishes the reference current for the SRCCLK pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. Analog Ground pin for Core PLL 3.3V Analog Power pin for Core PLL "Complememtary" clocks of differential pair CPU outputs. These open drain outputs need an external 1.5V pull-up. True clock of differential pair CPU outputs. These open drain outputs need an external 1.5V pull-up. Ground pin for the CPU outputs True clock of differential pair CPU outputs. These open drain outputs need an external 1.5V pull-up. Ground pin. Complement clock of differential pair for S-ATA support. +/- 300ppm accuracy required. True clock of differential pair for S-ATA support. +/- 300ppm accuracy required. Supply for SRC clocks, 3.3V nominal Ground pin for the IOAPIC outputs. IOAPIC clock outputs, norminal 2.5V. IOAPIC clock outputs, norminal 2.5V. Power pin for the IOAPIC outputs. 2.5V.
* Internal Pull-Up Resistor ** Internal Pull-Down Resistor ~ 1.5X Drive Strength
0813B--05/17/05
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Integrated Circuit Systems, Inc.
ICS952703 Preliminary Product Preview
General SMBus serial interface information for the ICS952703 How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) * ICS clock will acknowledge each byte one at a time * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * * * * * * * Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) starT bit T Slave Address D2(H) WR WRite Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
Index Block Read Operation
Controller (Host) T starT bit Slave Address D2(H) WR WRite Beginning Byte = N ACK RT Repeat starT Slave Address D3(H) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
ACK
ACK
Byte N + X - 1 ACK P stoP bit
Byte N + X - 1 N P Not acknowledge stoP bit
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ICS952703 Preliminary Product Preview
Table1: Frequency Selection Table
Bit4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit3 FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit2 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit0 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU MHz 200.00 200.01 200.97 190.11 100.00 100.00 100.99 95.00 166.66 166.65 161.59 151.97 133.33 133.34 133.98 126.66 206.02 210.00 214.06 217.90 103.01 105.00 106.99 109.01 164.66 167.91 171.22 174.38 137.32 140.00 142.67 145.33 SRC MHz 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 ZCLK MHz 133.33 133.34 133.98 126.74 133.33 133.34 134.66 126.66 133.33 133.32 129.27 121.57 133.33 133.34 133.98 126.66 137.35 140.00 142.70 145.27 137.35 140.00 142.65 145.35 131.73 134.33 136.98 139.50 137.32 140.00 142.67 145.33 AG P MHz 66.66 66.67 66.99 63.37 66.66 66.67 67.33 63.33 66.66 66.66 64.64 60.79 66.66 66.67 66.99 63.33 68.67 70.00 71.35 72.63 68.67 70.00 71.33 72.68 65.86 67.17 68.49 69.75 68.66 70.00 71.34 72.66 PCI MHz 33.33 33.33 33.49 31.69 33.33 33.33 33.66 31.67 33.33 33.33 32.32 30.39 33.33 33.33 33.49 31.67 34.34 35.00 35.68 36.32 34.34 35.00 35.66 36.34 32.93 33.58 34.24 34.88 34.33 35.00 35.67 36.33 Spread % 0.5% 0.35% 0.35% 0.35% 0.5% 0.35% 0.35% 0.35% 0.5% 0.35% 0.35% 0.35% 0.5% 0.35% 0.35% 0.35% 0.35% 0.35% 0.35% 0.35% 0.35% 0.35% 0.35% 0.35% 0.35% 0.35% 0.35% 0.35% 0.35% 0.35% 0.35% 0.35% down c enter c enter c enter down c enter c enter c enter down c enter c enter c enter down c enter c enter c enter c enter c enter c enter c enter c enter c enter c enter c enter c enter c enter c enter c enter c enter c enter c enter c enter
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ICS952703 Preliminary Product Preview
I C Table: Frequency Select Register
Byte 0 Bit Bit Bit Bit Bit Bit Bit Bit
2
2
Pin # -
Name SS_EN SEL12_48MHz SEL24_48MHz Bit4 FS3 FS2 FS1 FS0
Control Function Spread Enable Output Select Output Select Freq Select Bit 4 Freq Select Bit 3 Freq Select Bit 2 Freq Select Bit 1 Freq Select Bit 0
Type RW RW RW RW RW RW RW RW
0 OFF 48MHz 48MHz
1 ON 12MHz 24MHz
PWD 1 Latch Latch 0 Latch Latch Latch Latch
7 6 5 4 3 2 1 0
See Table1: Frequency Selection Table
I C Table: Output Control Register
Byte 1 Bit Bit Bit Bit Bit Bit Bit Bit
2
Pin # 2 3 4 43,42 14 15 16 17
Name REF0 REF1 REF2 SRCCLKT/C PCICLK_F0 PCICLK_F1 PCICLK0 PCICLK1
Control Function Output Control Output Control Output Control Output Control Output Control Output Control Output Control Output Control
Type RW RW RW RW RW RW RW RW
0 Disable Disable Disable Disable Disable Disable Disable Disable
1 Enable Enable Enable Enable Enable Enable Enable Enable
PWD 1 1 1 1 1 1 1 1
7 6 5 4 3 2 1 0
I C Table: Output Control Register
Byte 2 Bit Bit Bit Bit Bit Bit Bit Bit
2
Pin # 20 21 22 23 26 27 30 31
Name PCICLK2 PCICLK3 PCICLK4 PCICLK5 24_48MHz 12_48MHz AGPCLK1 AGPCLK0
Control Function Output Control Output Control Output Control Output Control Output Control Output Control Output Control Output Control
Type RW RW RW RW RW RW RW RW
0 Disable Disable Disable Disable Disable Disable Disable Disable
1 Enable Enable Enable Enable Enable Enable Enable Enable
PWD 1 1 1 1 1 1 1 1
7 6 5 4 3 2 1 0
I C Table: Output Control Register
Byte 3 Bit 7 Bit 6 Bit Bit Bit Bit Bit Bit 5 4 3 2 1 0 Pin # Name Reserved Reserved IREF Bit1 IREF Bit0 Vendor_ID3 Vendor_ID2 Vendor_ID1 Vendor_ID0 Control Function Reserved Reserved IREF Mulitiplier Programming Bits Type RW RW RW RW RW RW RW RW 0 00 = 5 x Iref 01 = 4 x Iref 1 10 = 6 x Iref 11 = 7 x Iref PWD 1 0 1 0 0 0 0 1
Vendor ID
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I C Table: Output Skew Control Register
Byte 4 Bit Bit Bit Bit Bit Bit Bit Bit
2
2
Pin # -
Name PCISkw3 PCISkw2 PCISkw1 PCISkw0 AGPSkw3 AGPSkw2 AGPSkw1 AGPSkw0
Control Function CPU-PCI 7 Step Skew Control (ps)
Type
0 0000:0 0001:N/A 0010:N/A 0011:N/A 0000:0 0001:N/A 0010:N/A 0011:N/A 0100:150 0101:N/A 0110:N/A 0111:N/A 0100:150 0101:N/A 0110:N/A 0111:N/A
1 1000:300 1001:N/A 1010:N/A 1011:N/A 1000:300 1001:N/A 1010:N/A 1011:N/A 1100:450 1101:600 1110:750 1111:900 1100:450 1101:600 1110:750 1111:900
PWD X X X X X X X X
7 6 5 4 3 2 1 0
RW RW RW RW RW CPU-AGP 7 Step Skew RW Control (ps) RW RW
I C Table: Output Divider Control Register
Byte 5 Bit Bit Bit Bit Bit Bit Bit Bit
2
Pin # -
Name ZCLKDiv3 ZCLKDiv2 ZCLKDiv1 ZCLKDiv0 AGPDiv3 AGPDiv2 AGPDiv1 AGPDiv0
Control Function ZCLK Divider Ratio Programmaing Bits
Type RW RW RW RW RW RW RW RW 0000:/2 0001:/3 0010:/5 0011:/7 0000:/2 0001:/3 0010:/5 0011:/7
0 0100:/4 0101:/6 0110:/10 0111:/14 0100:/4 0101:/6 0110:/10 0111:/14 1000:/8 1001:/12 1010:/20 1011:/28 1000:/8 1001:/12 1010:/20 1011:/28
1 1100:/16 1101:/24 1110:/40 1111:/56 1100:/16 1101:/24 1110:/40 1111:/56
PWD X X X X X X X X
7 6 5 4 3 2 1 0
AGP Divider Ratio Programmaing Bits
I C Table: Output Drive Control Register
Byte 6 Bit Bit Bit Bit Bit Bit Bit Bit
2
Pin # -
Name PCIStr1 PCIStr0 PCIStr1 PCIStr0 PCIStr1 PCIStr0 AGPStr1 AGPStr0
Control Function PCICLKF (1:0) Strength Control PCICLK (2:0) Strength Control PCICLK (5:3) Strength Control AGPCLK Strength Control
Type RW RW RW RW RW RW RW RW
0 00 = 0.63X 01 = 0.75X 00 = 0.63X 01 = 0.75X 00 = 0.63X 01 = 0.75X 00 = 0.70X 01 = 0.80X
1 10 = 0.88X 11 = 1.00X 10 = 0.88X 11 = 1.00X 10 = 0.88X 11 = 1.00X 10 = 0.90X 11 = 1.00X
PWD 1 1 1 1 1 1 1 1
7 6 5 4 3 2 1 0
I C Table: Reserved Register
Byte 7 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Type RW RW RW RW RW RW RW RW 0 1 PWD 1 1 1 1 1 1 1 1
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I C Table: Byte Count Register
Byte 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
2
2
Pin # -
Name BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0
Control Function
Type RW RW RW
0
1
PWD 0 0 0
Byte Count Programming b(7:0)
RW RW RW RW RW
Writing to this register will configure how many bytes will be read back, default is 0F = 15 bytes.
0 1 1 1 1
I C Table: WD Time Control & Async Frequency Selection Register
Byte 9 Bit Bit Bit Bit 7 6 5 4 Pin # Name Reserved ASYNC1 ASYNC0 Reserved WDTCtrl WD2 WD1 WD0 Control Function Reserved Fix PLL Async Freq Programming bits Reserved Watch Dog Time base Control WD Timer Bit 2 WD Timer Bit 1 WD Timer Bit 0 Type RW RW RW RW RW RW RW RW 0 1 PWD 0 0 0 0 0 1 1 1
See Table 2: Asynchronous Frequency Selection Table Reserved Reserved 290ms Base 1160ms Base
Bit 3 Bit 2 Bit 1 Bit 0
These bits represent X*290ms (or 1.16S) the watchdog timer waits before it goes to alarm mode. Default is 7 X 290ms = 2s.
Table 2: Asynchronous Frequency Selection Table
B9 bit6 0 0 1 1 B9 bit5 0 1 0 1 SRC ZCLK AGP PCI Main PLL 33.33 37.5 40 Main PLL Main PLL Main PLL 100 133.33 66.66 100 150.00 75 100 133.33 80
I C Table: VCO Control Select Bit & WD Timer Control Register
Byte 10 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name M/NEN WDEN WDStatus WD SF4 WD SF3 WD SF2 WD SF1 WD SF0 Control Function M/N Programming Enable Watchdog Enable WD Alarm Status Type RW RW R RW RW RW RW RW 0 Disable Disable Normal 1 Enable Enable Alarm PWD 0 0 0 0 0 0 0 0
2
Watch Dog Safe Freq Programming bits
Writing to these bit will configure the safe frequency as Byte0 bit (4:0).
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I C Table: VCO Frequency Control Register
Byte 11 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
2
2
Pin # -
Name N Div8 N Div9 M Div5 M Div4 M Div3 M Div2 M Div1 M Div0
Control Function N Divider Prog bit 8 N Divider Prog bit 9
Type RW RW RW
0
1
PWD X X X X X X X X
The decimal representation of M and N Divier in Byte 11 and 12 will configure the RW VCO frequency. Default at power up = latch-in or Byte 0 Rom table. M Divider Programming RW bits RW VCO Frequency = 14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2] RW RW
I C Table: VCO Frequency Control Register
Byte 12 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
2
Pin # -
Name N Div7 N Div6 N Div5 N Div4 N Div3 N Div2 N Div1 N Div0
Control Function
Type RW RW RW
0
1
PWD X X X X X X X X
The decimal representation of M and N Divier in Byte 11 and 12 will configure the N Divider Programming RW VCO frequency. Default at power up = b(7:0) latch-in or Byte 0 Rom table. RW RW VCO Frequency = 14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2] RW RW
I C Table: Spread Spectrum Control Register
Byte 13 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
2
Pin # -
Name SSP7 SSP6 SSP5 SSP4 SSP3 SSP2 SSP1 SSP0
Control Function
Type RW RW RW
0
1
PWD X X
Spread Spectrum Programming b(7:0)
RW RW RW RW RW
These Spread Spectrum bits in Byte 13 and 14 will program the spread pecentage. It is recommended to use ICS Spread % table for spread programming.
X X X X X X
I C Table: Spread Spectrum Control Register
Byte 14 Bit 7 Bit 6 Bit Bit Bit Bit Bit Bit 5 4 3 2 1 0 Pin # Name Reserved SSP14 SSP13 SSP12 SSP11 SSP10 SSP9 SSP8 Control Function Reserved Type R RW RW RW RW RW RW RW These Spread Spectrum bits in Byte 13 and 14 will program the spread pecentage. It is recommended to use ICS Spread % table for spread programming. 0 1 PWD 0 X X X X X X X
Spread Spectrum Programming b(14:8)
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Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 4.6 V 3.6V GND -0.5 V to VDD +0.5 V 0C to +70C -65C to +150C 115C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage V DD = 3.3 V +/-5% (unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Power Down Supply Current Input frequency Input Capacitance1 Transition Time1 Clk Stabilization1 Skew1
1
SYMBOL CONDITIONS MIN 2 V IH VIL VSS - 0.3 VIN = VDD I IH IIL1 VIN = 0 V; Inputs with no pull-up resistors -5 IIL2 VIN = 0 V; Inputs with pull-up resistors -200 IDD(op) IDDPD Fi CIN CINX Ttrans TSTAB TCPU-PCI CL = 0 pF; Select @ 100MHz CL = 0 pF; With input address to Vdd or GND VDD = 3.3 V; Logic Inputs X1 & X2 pins To 1st crossing of target Freq. From VDD = 3.3 V to 1% target Freq. VT = 1.5 V 27
TYP
MAX UNITS VDD + 0.3 V 0.8 V 5 mA mA mA 180 40 mA mA MHz pF pF ms ms ns
11
16 5 45 3 3 4
1.5
Guaranteed by design, not 100% tested in production.
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Electrical Characteristics - CPUCLKT/C
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Current Source V O = Vx Zo1 Output Impedance IOH = -1 mA Output High Voltage VOH3 IOL = 1 mA Output Low Voltage VOL3 VOL = 0.175V, VOH = 0.525V Rise Time t r3 VOH = 0.175V VOL = 0.525V Fall Time t f3 VT = 50% Duty Cycle dt3 VT = 50% Skew t sk3 1 VT = 50% Jitter, Cycle to cycle tjcyc-cyc MIN 3000 2.4 175 175 45 0.4 700 700 55 100 150 TYP MAX UNITS V ps ps % ps ps
Electrical Characteristics - PCICLK
TA = 0 - 70C; VDD = 3.3 V,+/-5%; CL = 30 pF PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time Skew
1 1 1
SYMBOL VOH1 VOL1 IOH1 I OL1 t r1 t f1 dt1 t sk1 tjcyc-cyc tjabs1
1
CONDITIONS IOH = -18 mA IOL = 9.4 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 2.1
TYP
16
MAX UNITS V 0.4 V -22 mA 57 mA 2 2 ns ns % ps ps ps
Duty Cycle
45
55 500 500 500
Jitter
1
Guaranteed by design, not 100% tested in production.
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Integrated Circuit Systems, Inc.
ICS952703 Preliminary Product Preview
Electrical Characteristics - AGPCLK
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER Output Frequency Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter SYMBOL FO1 RDSP11 VOH1 VOL1 IOH1 I OL1 tr11 tf11 dt11 t sk11 tjcyc-cyc 1 IOH = -1 mA IOL = 1 mA V OH@MIN = 1.0 V, V OH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V 3V66 CONDITIONS VO = VDD*(0.5) MIN 12 2.4 -33 30 0.5 0.5 45 0.55 -33 38 2 2 55 250 250 TYP MAX UNITS MHz 55 V V mA mA ns ns % ps ps
Electrical Characteristics - REF
TA = 0 - 70C; VDD = 3.3 V , +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time
1 1
SYMBOL VOH5 VOL5 IOH5 I OL5 t r5 t f5 dt5 tjcyc-cyc5 tjabs5
CONDITIONS IOH = -12 mA IOL = 9 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 2.6
TYP
16
MAX UNITS V 0.4 V -22 mA mA 4 4 ns ns % ps ps
Duty Cycle Jitter1
45
55 1000 800
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Integrated Circuit Systems, Inc.
ICS952703 Preliminary Product Preview
Electrical Characteristics - ZCLK
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER Output Frequency Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter SYMBOL FO1 RDSP11 VOH1 VOL1 IOH1 I OL1 tr11 tf11 dt11 t sk11 tjcyc-cyc 1 IOH = -1 mA IOL = 1 mA V OH@MIN = 1.0 V, V OH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V CONDITIONS VO = VDD*(0.5) MIN 12 2.4 -33 30 0.5 0.5 45 0.55 -33 38 2 2 55 250 250 TYP MAX UNITS MHz 55 V V mA mA ns ns % ps ps
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Integrated Circuit Systems, Inc.
ICS952703 Preliminary Product Preview
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Programming Header Via to Gnd Device Pad
Via to VDD 2K W
8.2K W Clock trace to load Series Term. Res.
Fig. 1
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Integrated Circuit Systems, Inc.
ICS952703 Preliminary Product Preview
PCI_STOP# - Assertion (transition from logic "1" to logic "0") The impact of asserting the PCI_STOP# signal will be the following. All PCI and stoppable PCI_F clocks will latch low in their next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next rising edge.
Assertion of PCI_STOP# Waveforms
PCI_STOP# PCI_F 33MHz PCI 33MHz
tsu
CPU_STOP# - Assertion (transition from logic "1" to logic "0") The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I2C configuration to be stoppable via assertion of CPU_STOP# are to be stopped after their next transition following the two CPU clock edge sampling as shown. The final state of the stopped CPU signals is CPUT=Low and CPUC=High. There is to be no change to the output drive current values. The CPUT will be driven high with a current value equal to (MULTSEL0) X (I REF), the CPUC signal will not be driven. Assertion of CPU_STOP# Waveforms
CPU_STOP# CPUT CPUC
CPU_STOP# Functionality
CPU_STOP# 1 0
CPUT Normal iref * Mult
CPUC Normal Float
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Integrated Circuit Systems, Inc.
ICS952703 Preliminary Product Preview
N
c
SYMBOL
L
E1 INDEX AREA
E
12 h x 45 D
A A1
A A1 b c D E E1 e h L N
In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8 VARIATIONS D mm. MIN MAX 15.75 16.00
In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
-Ce
b SEATING PLANE .10 (.004) C
N 48
10-0034
D (inch) MIN .620 MAX .630
Reference Doc.: JEDEC Publication 95, MO-118
Ordering Information
ICS952703yFLFT
Example:
ICS 95XXXX y F LF - T
Designation for tape and reel packaging RoHS Compliant Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
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Integrated Circuit Systems, Inc.
ICS952703 Preliminary Product Preview
Revision History
Rev. B Issue Date Description 5/17/2005 Added LF Ordering Information Page # 16
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